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个人信息：Personal Information
教授
性别：男
毕业院校：beoplay体育提现
学历：博士研究生毕业
学位：博士学位
在职信息：在岗
所在单位：集成电路学部
学科：微电子学与固体电子学
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论文成果
当前位置: 中文主页 >> bepaly手机下载 >> 论文成果- [21]A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor.MICROELECTRONICS JOURNAL.2016,51 :30-37
- [22]A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0. 18 mu m CMOS.MICROELECTRONICS JOURNAL.2016,57 :26-33
- [23]A Floating Buck Controlled Multi-Mode Dimmable LED Driver Using a Stacked NMOS Switch.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2015,62 (10):2584-2593
- [24]An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 mu m CMOS.MICROELECTRONICS JOURNAL.2016,52 :23-30
- [25]A linear and wide dynamic range transimpedance amplifier with adaptive gain control technique.Analog Integrated Circuits and Signal Processing.2017,90 (1):217-226
- [26]High voltage detection circuit for power over the ethernet.Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University.2015,42 (4):192-197
- [27]High-performance programmable charge pump for low voltage PLLs.Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University.2016,43 (2):186-192
- [28]A background split algorithm for high speed pipelined ADCs.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2016,88 (1):173-180
- [29]ECG front-end subsystem with the driven-right-leg circuit.Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University.2016,43 (4):166-171
- [30]Optimum design of the MDAC circuit for the 8 bit 80 MS/s pipelined A/D converter.Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University.2016,43 (1):162-166 and
- [31]A 0.45 V, Nano-Watt 0.033% Line Sensitivity MOSFET-Only Sub-Threshold Voltage Reference With no Amplifiers.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2016,63 (9):1370-1380
- [32]A high speed four-stage operational amplifier in 65 nm CMOS.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2016,86 (1):133-140
- [33]A high speed four-stage operational amplifier in 65 nm CMOS.Analog Integrated Circuits and Signal Processing.2016,86 (1):133-140
- [34]High efficiency two-step capacitor switching scheme for SAR ADC.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2016,86 (1):127-131
- [35]High efficiency two-step capacitor switching scheme for SAR ADC.Analog Integrated Circuits and Signal Processing.2016,86 (1):127-131
- [36]Trade-off between energy and linearity switching scheme for SAR ADC.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2016,86 (1):121-125
- [37]Trade-off between energy and linearity switching scheme for SAR ADC.Analog Integrated Circuits and Signal Processing.2016,86 (1):121-125
- [38]Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone.IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY.2015,5 (8):1093-1099
- [39]An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2015,83 (1):103-109
- [40]An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65聽nm CMOS.Analog Integrated Circuits and Signal Processing.2015,83 (1):103-109