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个人信息：Personal Information
教授
性别：男
毕业院校：beoplay体育提现
学历：博士研究生毕业
学位：博士学位
在职信息：在岗
所在单位：集成电路学部
学科：微电子学与固体电子学
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论文成果
当前位置: 中文主页 >> bepaly手机下载 >> 论文成果- [1]99.2% energy saving and high-linearity switching method for SAR ADCs.Analog Integrated Circuits and Signal Processing.2017,91 (1):93-96
- [2]A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture.MICROELECTRONICS JOURNAL.2015,46 (9):795-800
- [3]A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 mu m CMOS.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2015,62 (3):689-696
- [4]Effectiveness of p plus Layer in Mitigating Substrate Noise Induced by Through-Silicon Via for Microwave Applications.IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS.2016,26 (9):687-689
- [5]A low-distortion CMOS analogue voltage follower for high-speed ADCs.MICROELECTRONICS JOURNAL.2016,54 :67-71
- [6]A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS.2015,62 (7):621-625
- [7]Analysis of non-ideal factors and digital calibration for highresolution SAR ADCs.Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University.2015,42 (6):61-65 and 8
- [8]A Startup Robust Feedback Class-C VCO With Constant Amplitude Control in 0.18 mu m CMOS.IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS.2015,25 (8):541-543
- [9]A 0.5-V 1.3-mu W Analog Front-End CMOS Circuit.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS.2016,63 (6):523-527
- [10]Energy-efficient common-mode voltage switching scheme for SAR ADCs.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2016,89 (2):499-506
- [11]Thermo-Mechanical Characterization of Single-Walled Carbon Nanotube (SWCNT)-Based Through-Silicon via (TSV) in (100) Silicon.NANOSCIENCE AND NANOTECHNOLOGY LETTERS.2015,7 (6):481-485
- [12]Modeling and Optimization of Multiground TSVs for Signals Shield in 3-D ICs.IEEE Transactions on Electromagnetic Compatibility.2017,59 (2):461-467
- [13]A background fast convergence algorithm for timing skew in time-interleaved ADCs.MICROELECTRONICS JOURNAL.2016,47 :45-52
- [14]An Improved-Linearity, Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range.CIRCUITS SYSTEMS AND SIGNAL PROCESSING.2016,35 (12):4550-4566
- [15]A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semicon.IET Circuits, Devices and Systems.2014,8 (6):427-434
- [16]A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for biomedical applications.Microelectronics Journal.2017,59 :40-46
- [17]Analysis and optimization of the two-stage pipelined SAR ADCs.MICROELECTRONICS JOURNAL.2016,47 :40-44
- [18]Analysis and optimization of the two-stage pipelined SAR ADCs.Microelectronics Journal.2016,47 :40-44
- [19]Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING.2015,85 (2):373-377
- [20]A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC.MICROELECTRONICS JOURNAL.2015,46 (5):333-342