载波同步中数字锁相环的重构设计

doi:10.16180/j.cnki.issn1007-7820.2019.08.009

Abstract

Abstract:

Aiming at the problem that the development efficiency of the code or device in the previous carrier synchronous phase-locked loop is inherited and non-portable, a scheme of reconfiguring carrier synchronous PLLs in the form of reusing FPGA components was proposed. The scheme extracted the common modules of different phase-locked loops through functional decomposition, mapped suitable algorithms for functional modules and implemented them in FPGA. The method used the OCP protocol to encapsulate the interface to generate the FPGA component, and finally reused component to construct a new phase-locked loop application. The simulation results showed that the component reuse rate exceeded 60%, proving the correctness and effectiveness of the new method.

Key words: reconfiguration, digital PLL, carrier synchronous, component, OCP, FPGA

CLC Number:

TN876.4

DUAN Tie,HUANG Yan,WANG Yang. Reconfiguration Design of Digital PLL in Carrier Synchronous[J].Electronic Science and Technology, 2019, 32(8): 41-45.

Figures/Tables 8

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References 16

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功能模块	算法映射	实体化
乘法器	乘法	乘法器IP核
低通滤波器	FIR滤波器	FIR低通滤波器
低通滤波器	IIR滤波器	IIR低通滤波器
鉴相器	Costas鉴相器	符号判决、取反
	判决反馈环鉴相器	积分、抽样、符号判决
	平方环鉴相器	乘法器和低通滤波器
	DD锁相环	求门限值、符号判决、移位加法
环路滤波器	一阶环	仅实体化二阶环
	二阶环
	三阶环
NCO	查找表	DDS IP核
NCO	CORDIC算法	CORDIC IP核
平方变换	乘法	乘法器IP核
2分频模块	乘法	乘法器IP核
带通滤波器	IIR滤波器	IIR带通滤波器

编号	组件	位宽/bit		连接序号		组件参数
编号	组件	输入	输出	输入	输出	组件参数
1	鉴相器	32	32	4,5	3	——
2	DDS	32	8	3	6,7	频率字更新周期 R_F=8CLK
3	环路滤波器	32	32	1	2	系数:C₁=2^-5, C₂=2^-12
4	FIR低通滤波器1	16	32	6	1	系数:15,-22,-76, 129,511,511,129, -76,-22,15
5	FIR低通滤波器2	16	32	7	1	同上
6	乘法器1	8	16	2	4	——
7	乘法器2	8	16	2	5	——

锁相环	捕获时间/ms		测试信号	信号参数
锁相环	传统方式	重构方式	测试信号	码速率	采样率	载波	频偏
Costas环	0.60	0.61	BPSK	4 MHz	32 MHz	70 MHz	23.4 kHz
判决反馈环	0.33	0.42	QPSK	1 MHz	8 MHz	2 MHz	0.5 kHz
平方环	0.98	1.07	MSK	1 MHz	16 MHz	3 MHz	23.4 kHz
DD锁相环	12.50	13.23	QAM	1 MHz	8 MHz	2 MHz	1 kHz

组件	Costas环	判决反馈环	平方环	DD锁相环
乘法器	√	√	√	√
FIR低通滤波器	√	√		√
IIR低通滤波器			√
Costas鉴相器	√
判决反馈环鉴相器		√
DD鉴相器				√
环路滤波器	√	√	√	√
IIR带通滤波器			√
DDS组件	√	√	√
CORDIC 组件				√
复用率	——	80%	60%	60%

Reconfiguration Design of Digital PLL in Carrier Synchronous

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