Abstract:

Matrix inversion is a basic problem in engineering calculation. In large-scale MIMO systems, array signal processing, image signal processing and other applications, the processing speed of large-scale matrix inversion is very important to the system performance. However, the traditional matrix inversion method has high computational complexity, low parallelism and consumes a lot of storage space, which is not conducive to hardware acceleration. Aiming at the hardware acceleration problem of large-scale matrix inversion, this study studies the matrix inversion algorithm based on LDL decomposition and proposes a large-scale matrix inversion acceleration architecture based on this algorithm. Using the characteristic that the diagonal elements of triangular matrix after LDL decomposition are all 1, the matrix is designed by block iteration, which reduces the amount of calculation and improves the calculation speed. This study designs and implements the accelerator based on Xilinx Virtex7 FPGA. The experimental results show that under the 128 order matrix, the throughput is 105.2 Inv·s^-1 and the maximum clock frequency is 200 MHz. Compared with the existing matrix inversion acceleration scheme, this design occupies less hardware resources and has higher performance.

Key words: LDL decomposition, matrix inversion, Cholesky decomposition, matrix block, triangular matrix transformation, matrix multiplication, hardware acceleration, field programmable gate array