基于FPGA的多功能阵列信号处理系统设计

doi:10.16180/j.cnki.issn1007-7820.2023.03.001

Abstract

Abstract:

In order to adapt to the characteristics of high real-time performance and large computation of the array signal processing system, this study proposes a multifunctional array signal processing system based on FPGA. By using advanced large-scale high-performance FPGA and multichannel high-precision ADC chips, the synchronous acquisition and digital down conversion processing of 40 intermediate frequency signals can be accomplished, and 36 sets of beam data can be obtained by digital beamforming. By configuring various types of external interfaces, the network data interaction, serial port control, beam control and MGT high-speed data transmission can be achieved. In this study, the hardware and software architecture of the system is presented, and the chip models, peripheral interface and the realization method of each software function module are introduced in detail. The measurement results indicate that the system meets the design requirements, has a strong array signal processing capabilities and good versatility and scalability.

Key words: multifunction, array signal processing, FPGA, ADC, digital down conversion, digital beamforming, beam control, high-speed transmission

CLC Number:

TP274.2

LUO Xin,FENG Wu,SUN Weijie,LIU Maliang. Design of Multifunctional Array Signal Processing System Based on FPGA[J].Electronic Science and Technology, 2023, 36(3): 1-6.

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References 19

[1]	杨涛, 朱闪闪, 刘玉佼. 阵列信号处理实验平台设计[J]. 电气电子教学学报, 2015(2):103-105.
	Yang Tao, hu Shanshan, Liu Yujiao. ZDesign on experimental platform for array signal processing[J]. Journal of Electrical & Electronic Education, 2015(2):103-105.
[2]	张涛, 庞鹏翔, 董加伟. 基于阵列信号处理的一体化模块设计[J]. 信息技术与网络安全, 2015, 34(9):59-61.
	Zhang Tao, Pang Pengxiang, Dong Jiawei. Design of a novel array antenna signal processing unit[J]. Information Technology and Network Security, 2015, 34(9):59-61.
[3]	周成伟, 郑航, 顾宇杰, 等. 互质阵列信号处理研究进展:波达方向估计与自适应波束成形[J]. 雷达学报, 2019, 8(5):558-577.
	Zhou Chengwei, Zheng Hang, Gu Yujie, et al. Research progress on coprime array signal processing:Direction-of-Arrival estimation and adaptive beamforming[J]. Journal of Radars, 2019, 8(5):558-577.
[4]	耿昭谦, 朱虎明, 李旭明, 等. 基于高性能计算的雷达信号处理研究综述[J]. 电子科技, 2021, 34(9):1-6.
	Geng Zhaoqian, Zhu Huming, Li Xuming, et al. A review: Radar signal processing based on high performance computing[J]. Electronic Science and Technology, 2021, 34(9):1-6.
[5]	杨亮, 于宗光, 魏敬和, 等. 多通道阵列信号处理可重构异构SoC设计[J]. 微电子学, 2018, 48(5):648-651.
	Yang Liang, Yu Zongguang, Wei Jinghe, et al. Design of reconfigurable heterogeneous SoC for multi-channel array signal processing[J]. Microelectronics, 2018, 48(5):648-651.
[6]	杨欣然, 吴琼之, 范秋香. 多通道实时阵列信号处理系统的设计[J]. 电子设计工程, 2015(12):176-179.
	Yang Xinran, Wu Qiongzhi, Fan Qiuxiang. Design of multi-channel real-time array signal processing system[J]. Electronic Design Engineering, 2015(12):176-179.
[7]	张静. 某雷达信号处理板的硬件设计与实现[J]. 电子科技, 2015, 28(6):147-149.
	Zhang Jing. The hardware system design of a certain radar signal processing board[J]. Electronic Science and Technology, 2015, 28(6):147-149.
[8]	朱启强, 郑容秋. 实时阵列信号处理系统设计[J]. 信息技术与网络安全, 2014(24):25-27.
	Zhu Qiqiang, Zheng Rongqiu. Real-time processing system design on array signal[J]. Information Technology and Network Security, 2014(24):25-27.
[9]	杨欣然. 实时阵列信号处理系统的设计与实现[D]. 北京: 北京理工大学, 2015.
	Yang Xinran. Design and implementation of real-time array signal processing system[D]. Beijing: Beijing Institute of Technology, 2015.
[10]	姜婕. 基于多DSP的雷达信号处理任务分配与实现[J]. 电子科技, 2017, 30(5):83-86.
	Jiang Jie. Task assignment and realization of radar signal processing based on Multi-DSP[J]. Electronic Science and Technology, 2017, 30(5):83-86.
[11]	Xilinx. 7 Series FPGAs packaging and pinout product specification[M]. San Jose: Xilinx, 2021.
[12]	金恒康, 张一闻. 基于Zynq的麦克风阵列同步高速采集系统设计[J]. 电子科技, 2019, 32(7):28-32.
	Jin Hengkang, Zhang Yiwen. Research on design of synchronous high speed acquisition system of microphone array based on Zynq[J]. Electronic Science and Technology, 2019, 32(7):28-32.
[13]	雷雯, 栗敬雨. 基于四路ADC芯片交替采样的宽带信号采集系统设计[J]. 电子科技, 2021, 34(9):30-35.
	Lei Wen, Li Jingyu. Design of a sampling system based on four-channel ADC chip time-interleaved sampling[J]. Electronic Science and Technology, 2021, 34(9):30-35.
[14]	Texas Instruments. Octal-channel 14-bit 80-MSPS high-SNR and low-power ADC, check for samples: ADS5294[M]. Dallas: Texas Instruments, 2013.
[15]	WIZnet. High-performance internet connectivity solution,W5300[M]. Seoul:WIZnet, 2010.
[16]	陈凯, 唐清善, 李亚捷, 等. 基于FPGA的千兆以太网传输实现方案[J]. 电子科技, 2017, 30(6):102-104.
	Chen Kai, Tang Qingshan, Li Yajie, et al. Design method of gigabit Ethernet transmission based on FPGA[J]. Electronic Science and Technology, 2017, 30(6):102-104.
[17]	孙高俊, 刘志英. 基于FPGA的雷达IQ光纤数据采集及传输系统[J]. 电子科技, 2016, 29(4):169-172.
	Sun Gaojun, Liu Zhiying. Radar IQ fiber-optical data acquisition and transmission system based on FPGA[J]. Electronic Science and Technology, 2016, 29(4):169-172.
[18]	苗露. 高速多通道数字波束形成系统设计与实现[D]. 西安: beoplay体育提现, 2017.
	Miao Lu. Design and implementation of high-speedmulti-channel digital beamforming system[D]. Xi'an: Xidian University, 2017.
[19]	尹利忠, 孔繁, 耿东华, 等. 基于FPGA的一维多波束处理机设计[J]. 数字技术与应用, 2020, 38(1):155-157.
	Yin Lizhong, Kong Fan, Geng Donghua, et al. Research of situation awareness based on panorama vision[J]. Digital Technology and Application, 2020, 38(1):155-157.

Design of Multifunctional Array Signal Processing System Based on FPGA

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