基于FPGA的千兆以太网端口通信设计

doi:10.16180/j.cnki.issn1007-7820.2024.01.007

Abstract

Abstract:

In view of the problem of Ethernet transmission rate and real-time in embedded field, a design of Gigabit Ethernet port communication based on FPGA(Field Programmable Gate Array)is proposed. This study designs the forwarding function of Gigabit Ethernet switch, and implements end-to-end data communication based on label forwarding. Datagrams with label are sent by CPU(Central Processing Unit), and are outputted through Gigabit Ethernet interface, and are sent to FPGA through RGMII(Reduced Gigabit Media Independent Interface)port. FPGA judges output port number field in label through internal logic and removes label, and outputs datagrams to connecting device from corresponding Gigabit Ethernet interface. Peripherals input datagrams through Gigabit Ethernet ports, and send datagrams to FPGA through SGMII(Serial Gigabit Media Independent Interface) protocol. FPGA adds labels through internal logic and outputs them to CPU through polling, so as to realize interworking of connecting devices of multiple Gigabit Ethernet interface. The experimental results reveal the feasibility and effectiveness of the FPGA logic. The transmission rate reaches 1 Gbit·s^-1, the datagrams forwarding delay is less than 100 μs, and the packet loss rate is 0%,which indicates that the data transmission stability is high, and the proposed design meets the actual needs of existing projects.

Key words: FPGA, Gigabit Ethernet, ethernet switch, label, CPU, datagram, RGMII interface, SGMII protocol

CLC Number:

TN79

LAN Wei,HAN Yanzhe,HU Xiao. Design of Gigabit Ethernet Port Communication Based on FPGA[J].Electronic Science and Technology, 2024, 37(1): 48-54.

Figures/Tables 14

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报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
64 Byte	1	Port1	43 940 420	Port1	43 940 420
64 Byte	2	Port2	43 952 750	Port2	43 952 750
128 Byte	1	Port1	25 360 198	Port1	25 360 198
128 Byte	2	Port2	25 367 404	Port2	25 367 404
256 Byte	1	Port1	13 557 633	Port1	13 557 633
256 Byte	2	Port2	13 561 408	Port2	13 561 408
512 Byte	1	Port1	7 072 744	Port1	7 072 744
512 Byte	2	Port2	7 074 867	Port2	7 074 867
1 024 Byte	1	Port1	3 602 208	Port1	3 602 208
1 024 Byte	2	Port2	3 603 231	Port2	3 603 231
1 518 Byte	1	Port1	2 465 186	Port1	2 465 186
1 518 Byte	2	Port2	2 465 862	Port2	2 465 862
64~1 518 Byte	1	Port1	4 628 442	Port1	4 628 442
64~1 518 Byte	2	Port2	4 629 743	Port2	4 629 743

报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
64 Byte	1	Port1	44 180 999	Port1	44 180 999
64 Byte	2	Port2	44 193 895	Port2	44 193 895
128 Byte	1	Port1	250 861 16	Port1	25 086 116
128 Byte	2	Port2	25 112 629	Port2	25 112 629
256 Byte	1	Port1	13 619 989	Port1	13 619 989
256 Byte	2	Port2	13 624 174	Port2	13 624 174
512 Byte	1	Port1	7 087 625	Port1	7 087 625
512 Byte	2	Port2	7 095 127	Port2	7 095 127
1 024 Byte	1	Port1	3 632 905	Port1	3 632 905
1 024 Byte	2	Port2	3 634 170	Port2	3 634 170
1 518 Byte	1	Port1	2 447 469	Port1	2 447 469
1 518 Byte	2	Port2	2 448 281	Port2	2 448 281
64~1 518 Byte	1	Port1	4 589 117	Port1	4 589 117
64~1 518 Byte	2	Port2	4 590 811	Port2	4 590 811

报文长度	报文流	Average /μs	Min /μs	Max /μs
256 Byte	1	5.329	5.26	5.38
512 Byte	1	8.414	8.34	8.46
1 024 Byte	1	14.542	14.48	14.60
1 518 Byte	1	20.473	20.40	20.54
256~1 518 Byte	1	20.241	5.32	21.34

报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
256 Byte	1	Port1	13 619 989	Port1	13 619 989
256 Byte	2	Port2	13 624 174	Port2	13 624 174
512 Byte	1	Port1	7 087 625	Port1	7 087 625
512 Byte	2	Port2	7 095 127	Port2	7 095 127
1 024 Byte	1	Port1	3 632 905	Port1	3 632 905
1 024 Byte	2	Port2	3 634 170	Port2	3 634 170
1 518 Byte	1	Port1	2 447 469	Port1	2 447 469
1 518 Byte	2	Port2	2 448 281	Port2	2 448 281
256~1 518	1	Port1	4 165 308	Port1	4 165 308
Byte	2	Port2	4 167 222	Port2	4 167 222

Design of Gigabit Ethernet Port Communication Based on FPGA

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